module fpu_slicer
#
(
    parameter length_exp=8,
    length_val=23
)
(
    input [length_exp+length_val:0]op1,
    input [length_exp+length_val:0]op2,
    output sign1,
    output sign2,
    output [length_val-1:0]val1,
    output [length_val-1:0]val2,
    output [length_exp-1:0]exp1,
    output [length_exp-1:0]exp2,
    output [9:0]fclass_o,
    output fsignals1,
    output fsignals2

);

wire inf1,inf2,qnan1,qnan2,subn1,subn2,zero1,zero2,snan1,snan2;
assign sign1=op1[length_exp+length_val];
assign sign2=op2[length_exp+length_val];//(fullin-float to half->ftlout->go to calc)
assign exp1=op1[length_exp+length_val-1:length_val];
assign exp2=op2[length_exp+length_val-1:length_val];
assign val1=op1[length_val-1:0];
assign val2=op2[length_val-1:0];
//op status generation
assign qnan1=(val1!=0&(exp1=={length_exp{1'b1}})&(!val1[length_val-1]));//qNaN Gen
assign qnan2=(val2!=0&(exp2=={length_exp{1'b1}})&(!val2[length_val-1]));
assign snan1=(val1!=0&(exp1=={length_exp{1'b1}})&(val1[length_val-1]));//sNaN Gen
assign snan2=(val2!=0&(exp2=={length_exp{1'b1}})&(val2[length_val-1]));
assign inf1=(val1==0&(exp1=={length_exp{1'b1}}));//Inf Gen
assign inf2=(val2==0&(exp2=={length_exp{1'b1}}));
assign subn1=(exp1==0&val1!=0);
assign subn2=(exp2==0&val2!=0);
assign zero1=(exp1==0&val1==0);
assign zero2=(exp2==0&val2==0);
assign fclass_o={qnan1,snan1,inf1&(!sign1),(!sign1)&(!subn1),(!sign1)&subn1,
                zero1&(!sign1),zero1&sign1,sign1&(!subn1),sign1&subn1,inf1&sign1};
assign fsignals1={inf1,zero1,subn1,qnan1,snan1};
assign fsignals2={inf2,zero2,subn2,qnan2,snan2};
endmodule